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CYV15G0403TB
Independent Clock Quad HOTLink IITM Serializer
Features
* Second-generation HOTLink(R) technology * Compliant to SMPTE 292M and SMPTE 259M video standards * Quad channel video serializer -- 195- to 1500-Mbps serial data signaling rate -- Simultaneous operation at different signaling rates * Supports half-rate and full-rate clocking * Internal phase-locked loops (PLLs) with no external PLL components * Redundant differential PECL-compatible serial outputs per channel -- No external bias resistors required -- Signaling-rate controlled edge-rates * * * * * * * * -- Internal source termination Synchronous LVTTL parallel interface JTAG boundary scan Built-In Self-Test (BIST) for at-speed link testing Low-power 2W @ 3.3V typical Single 3.3V supply Thermally enhanced BGA Pb-Free package option available 0.25 BiCMOS technology
Functional Description
The CYV15G0403TB Independent Clock Quad HOTLink IITM Serializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. All four channels are independent and can simultaneously operate at different rates. Each channel accepts 10-bit parallel characters in an Input Register and converts them to serial data. Figure 1 illustrates typical connections between independent video co-processors and corresponding CYV15G0403TB Serializer and CYV15G0404RB Reclocking Deserializer chips. The CYV15G0403TB satisfies the SMPTE-259M and SMPTE-292M compliance as per SMPTE EG34-1999 Pathological Test Requirements. As a second-generation HOTLink device, the CYV15G0403TB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. Each channel of the CYV15G0403TB Quad HOTLink II device independently accepts scrambled 10-bit transmission characters. These characters are serialized and output from dual Positive ECL (PECL) compatible differential transmission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel. Each channel contains an independent BIST pattern generator. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit section of this device, each receive section of a connected HOTLink II device, and across the interconnecting links.
Figure 1. HOTLink IITM System Connections
Reclocked Outputs
10 10
10
Independent Channel CYV15G0403TB Serializer
Serial Links
Independent Channel CYV15G0404RB Reclocking Deserializer
10
10
10 10
Reclocked Outputs
Cypress Semiconductor Corporation Document #: 38-02104 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised May 2, 2007
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Video Coprocessor
Video Coprocessor
10
CYV15G0403TB
The CYV15G0403TB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include
multi-format routers, switchers, format converters, and cameras.
CYV15G0403TB Serializer Logic Block Diagram
REFCLKA
REFCLKB
REFCLKC
TXDA[9:0]
TXDB[9:0]
TXDC[9:0]
x10
Phase Align Buffer Serializer
x10 Phase Align Buffer Serializer TX
x10 Phase Align Buffer Serializer TX
x10 Phase Align Buffer Serializer TX
TX
OUTB1 OUTB2
OUTC1 OUTC2
Document #: 38-02104 Rev. *C
OUTD1 OUTD2
OUTA1 OUTA2
TXDD[9:0]
REFCLKD
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CYV15G0403TB
Serializer Path Block Diagram
REFCLKA+ REFCLKA- TXRATEA SPDSELA TXCLKOA TXERRA TXCLKA TXCKSELA 0 1 Character-Rate Clock A PABRSTA
Bit-Rate Clock A
= Internal Signal
TransmitPLL PLL Transmit Clock Multiplier A Clock Multiplier
OE[2..1]A
RESET
TXBISTA
OE[2..1]A
Phase-Align Phase-Align Buffer Buffer
BIST LFSR
Input Register
TXDA[9:0]
10
10
10
10
Shifter
OUTA1+ OUTA1- OUTA2+ OUTA2-
REFCLKB+ REFCLKB- TXRATEB SPDSELB TXCLKOB TXERRB TXCLKB TXCKSELB 0 1 Character-Rate Clock B PABRSTB
Bit-Rate Clock B
TransmitPLL PLL Transmit Clock Multiplier B Clock Multiplier
OE[2..1]B
TXBISTB
OE[2..1]B
Phase-Align Phase-Align Buffer Buffer
BIST LFSR
Input Register
TXDB[9:0]
10
10
10
10
Shifter
OUTB1+ OUTB1- OUTB2+ OUTB2-
REFCLKC+ REFCLKC- TXRATEC SPDSELC TXCLKOC TXERRC TXCLKC TXCKSELC 0 1 Character-Rate Clock C PABRSTC
Bit-Rate Clock C
TransmitPLL PLL Transmit Clock Multiplier C Clock Multiplier
OE[2..1]C
TXBISTC
OE[2..1]C
Phase-Align Phase-Align Buffer Buffer
BIST LFSR
Input Register
TXDB[9:0]
10
10
10
10
Shifter
OUTC1+ OUTC1- OUTC2+ OUTC2-
REFCLKD+ REFCLKD- TXRATED SPDSELD TXCLKOD TXERRD TXCLKD TXCKSELD 0 1 Character-Rate Clock D PABRSTD
Bit-Rate Clock D
TransmitPLL PLL Transmit Clock Multiplier D Clock Multiplier
OE[2..1]D
TXBISTD
OE[2..1]D
Phase-Align Phase-Align Buffer Buffer
BIST LFSR
Input Register
TXDD[9:0]
10
10
10
10
Shifter
OUTD1+ OUTD1- OUTD2+ OUTD2-
Document #: 38-02104 Rev. *C
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CYV15G0403TB
JTAG and Device Configuration and Control Block Diagram
TXRATE[A..D] TXCKSEL[A..D] PABRST[A..D] TXBIST[A..D] OE[2..1][A..D] GLEN[11..0] FGLEN[2..0]
= Internal Signal
RESET TRST
WREN ADDR[3:0] DATA[4:0]
Device Configuration and Control Interface
JTAG Boundary Scan Controller
TMS TCLK TDI TDO
Document #: 38-02104 Rev. *C
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CYV15G0403TB
Pin Configuration (Top View)[1]
1 A B C D E F G H J K L M N P R T U V W Y
NC
2
OUT C1- OUT C1+ TMS
3
NC
4
OUT C2- OUT C2+
5
VCC VCC VCC VCC
6
NC
7
OUT D1- OUT D1+
8
GND
9
GND
10
OUT D2- OUT D2+
11
GND
12
OUT A1- OUT A1+ DATA [1] DATA [0]
13
GND
14
GND
15
OUT A2- OUT A2+ SPD SELD
16
VCC VCC VCC VCC
17
VCC NC
18
OUT B1- OUT B1+ TRST
19
VCC NC
20
OUT B2- OUT B2+ TDO
VCC
TDI
VCC VCC VCC VCC
VCC NC
GND
NC
NC
GND
NC
VCC VCC VCC
NC
GND
NC
NC
DATA [3] DATA [2]
GND
NC
NC
GND
TCLK
RESET
VCC
SPD SELC
GND
GND
DATA [4]
GND
GND
NC
NC
NC
SCAN TMEN3 EN2
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
TX DC[0] TX DC[4]
NC
NC
NC
TX CLKOB SPD SELA
NC
TX DC[7]
WREN
TX DC[1]
SPD SELB
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
TX DC[9]
TX DC[5] REF CLKC- REF CLKC+
TX DC[2] TX DC[8]
TX DC[3] TX CLKC TX DC[6] TX ERRC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TX DB[6] TX CLKB
NC
NC
NC
REF REF CLKB+ CLKB-
TX ERRB
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
TX DB[5] TX DB[1]
TX DB[4] TX DB[0]
TX DB[3] TX DB[9]
TX DB[2] TX DB[7]
NC
TX CLKOC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TX DD[0] TX DD[3] TX DD[5] TX DD[6]
TX DD[1] TX DD[4] TX DD[7] TX CLKD
TX DD[2] TX DD[8]
TX DD[9]
VCC VCC VCC VCC
NC
NC
GND
TX DA[9]
ADDR REF [0] CLKD-
TX DA[1]
GND
TX DA[4] TX DA[3] TX DA[2] TX DA[0]
TX DA[8] TX DA[7] TX DA[6] TX DA[5]
VCC VCC VCC VCC
NC
TX DB[8]
NC
NC
NC
NC
NC
GND
NC
ADDR REF TX [2] CLKD+ CLKOA ADDR [1] NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
GND
ADDR [3] TX CLKOD
NC
TX ERRA
GND
NC
REF CLKA+ REF CLKA-
NC
NC
NC
NC
NC
NC
GND
TX CLKA
NC
GND
TX ERRD
NC
NC
Note 1. NC = Do not connect.
Document #: 38-02104 Rev. *C
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CYV15G0403TB
Pin Configuration (Bottom View)[1]
20 A B C D E F G H J K L M N P R T U V W Y
OUT B2-
19
VCC
18
OUT B1-
17
VCC
16
VCC
15
OUT A2-
14
GND
13
GND
12
OUT A1-
11
GND
10
OUT D2-
9
GND
8
GND
7
OUT D1-
6
NC
5
VCC
4
OUT C2-
3
NC
2
OUT C1-
1
NC
OUT B2+
NC
OUT B1+
NC
VCC
OUT A2+
NC
GND
OUT A1+
NC
OUT D2+
NC
GND
OUT D1+
VCC
VCC
OUT C2+
VCC
OUT C1+
VCC
TDO
GND
TRST
NC
VCC
SPD SELD
NC
GND
DATA [1]
DATA [3]
NC
NC
GND
NC
NC
VCC
VCC
VCC
TMS
TDI
TMEN3 SCAN EN2
NC
NC
VCC
NC
GND
GND
DATA [0]
DATA [2]
DATA [4]
GND
GND
SPD SELC
VCC
VCC
VCC
VCC
RESET
TCLK
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
TX CLKOB
NC
NC
NC
TX DC[0]
NC
NC
NC
SPD SELA
NC
SPD SELB
TX DC[1]
TX DC[4]
WREN
TX DC[7]
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
TX DC[3]
TX DC[2]
TX DC[5]
TX DC[9]
NC
NC
NC
NC
TX CLKC
TX DC[8]
REF CLKC-
NC
TX DB[6]
NC
NC
NC
TX DC[6]
NC
REF CLKC+
NC
TX CLKB
TX ERRB
REF REF CLKB- CLKB+
TX ERRC
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
TX DB[2]
TX DB[3]
TX DB[4]
TX DB[5]
NC
NC
NC
NC
TX DB[7]
TX DB[9]
TX DB[0]
TX DB[1]
NC
NC
TX CLKOC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
TX DB[8]
NC
VCC
TX DA[8]
TX DA[4]
GND
TX DA[1]
REF ADDR CLKD- [0]
TX DA[9]
GND
NC
NC
VCC
TX DD[9]
TX DD[2]
TX DD[1]
TX DD[0]
NC
NC
NC
NC
VCC
TX DA[7]
TX DA[3]
GND
TX REF ADDR CLKOA CLKD+ [2]
NC
GND
NC
NC
VCC
NC
TX DD[8]
TX DD[4]
TX DD[3]
NC
NC
REF CLKA+
NC
VCC
TX DA[6]
TX DA[2]
GND
TX ERRA
NC
ADDR [1]
ADDR [3]
GND
NC
NC
VCC
NC
NC
TX DD[7]
TX DD[5]
NC
NC
REF CLKA-
TX ERRD
VCC
TX DA[5]
TX DA[0]
GND
NC
TX CLKA
NC
TX CLKOD
GND
NC
NC
VCC
NC
NC
TX CLKD
TX DD[6]
Document #: 38-02104 Rev. *C
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CYV15G0403TB
Pin Definitions CYV15G0403TB Quad HOTLink II Serializer
Name TXDA[9:0] TXDB[9:0] TXDC[9:0] TXDD[9:0] I/O Characteristics Signal Description LVTTL Input, synchronous, sampled by the associated TXCLKx or REFCLKx[2] LVTTL Output, synchronous to REFCLKx [3], asynchronous to transmit channel enable / disable, asynchronous to loss or return of REFCLKx Transmit Data Inputs. TXDx[9:0] data inputs are captured on the rising edge of the transmit interface clock. The transmit interface clock is selected by the TXCKSELx latch via the device configuration interface. Transmit Path Data and Status Signals
TXERRA TXERRB TXERRC TXERRD
Transmit Path Error. TXERRx is asserted HIGH to indicate detection of a transmit Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted until the transmit Phase-Align Buffer is re-centered with the PABRSTx latch via the device configuration interface. When TXBISTx = 0, the BIST progress is presented on the associated TXERRx output. The TXERRx signal pulses HIGH for one transmit-character clock period to indicate a pass through the BIST sequence once every 511 character times. TXERRx is also asserted HIGH, when any of the following conditions is true: * The TXPLL for the associated channel is powered down. This occurs when OE2x and OE1x for a given channel are both disabled by setting OE2x = 0 and OE1x = 0. * The absence of the REFCLKx signal.
Transmit Path Clock Signals REFCLKA REFCLKB REFCLKC REFCLKD Differential LVPECL Reference Clock. REFCLKx clock inputs are used as the timing references for the or single-ended associated transmit PLL. These input clocks may also be selected to clock the transmit LVTTL input clock parallel interface. When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock source to either the true or complement REFCLKx input, and leave the alternate REFCLKx input open (floating). When driven by an LVPECL clock source, the clock must be a differential clock, using both inputs. LVTTL Clock Input, Transmit Path Input Clock. When configuration latch TXCKSELx = 0, the associated internal pull-down TXCLKx input is selected as the character-rate input clock for the TXDx[9:0] input. In this mode, the TXCLKx input must be frequency-coherent to its associated TXCLKOx output clock, but may be offset in phase by any amount. Once initialized, TXCLKx is allowed to drift in phase as much as 180 degrees. If the input phase of TXCLKx drifts beyond the handling capacity of the Phase Align Buffer, TXERRx is asserted to indicate the loss of data, and remains asserted until the Phase Align Buffer is initialized. The phase of the TXCLKx input clock relative to its associated REFCLKx is initialized when the configuration latch PABRSTx is written as 0. When the associated TXERRx is deasserted, the Phase Align Buffer is initialized and input characters are correctly captured. LVTTL Output Transmit Clock Output. TXCLKOx output clock is synthesized by each channel's transmit PLL and operates synchronous to the internal transmit character clock. TXCLKOx operates at either the same frequency as REFCLKx (TXRATEx = 0), or at twice the frequency of REFCLKx (TXRATEx = 1). The transmit clock outputs have no fixed phase relationship to REFCLKx. Asynchronous Device Reset. RESET initializes all state machines, counters, and configuration latches in the device to a known state. RESET must be asserted LOW for a minimum pulse width. When the reset is removed, all state machines, counters and configuration latches are at an initial state. As per the JTAG specifications the device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has to be reset separately. Refer to "JTAG Support" on page 12 for the methods to reset the JTAG state machine. See Table 2 on page 11 for the initialize values of the device configuration latches.
TXCLKA TXCLKB TXCLKC TXCLKD
TXCLKOA TXCLKOB TXCLKOC TXCLKOD
Device Control Signals RESET LVTTL Input, asynchronous, internal pull-up
Notes 2. When REFCLKx is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx. 3. When REFCLKx is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx.
Document #: 38-02104 Rev. *C
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CYV15G0403TB
Pin Definitions (continued) CYV15G0403TB Quad HOTLink II Serializer
Name SPDSELA SPDSELB SPDSELC SPDSELD I/O Characteristics Signal Description 3-Level Select[4] static control input Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range of each channel's PLL. LOW = 195-400 MBd MID = 400-800 MBd HIGH = 800-1500 MBd. Control Write Enable. The WREN input writes the values of the DATA[4:0] bus into the latch specified by the address location on the ADDR[3:0] bus.[5] Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to configure the device. The WREN input writes the values of the DATA[4:0] bus into the latch specified by the address location on the ADDR[3:0] bus.[5] Table 2 on page 11 lists the configuration latches within the device, and the initialization value of the latches upon the assertion of RESET. Table 3 on page 12 shows how the latches are mapped in the device. Control Data Bus. The DATA[4:0] bus is the input data bus used to configure the device. The WREN input writes the values of the DATA[4:0] bus into the latch specified by address location on the ADDR[3:0] bus.[5 ] Table 2 on page 11 lists the configuration latches within the device, and the initialization value of the latches upon the assertion of RESET. Table 3 on page 12 shows how the latches are mapped in the device. Transmit Clock Select. Transmit PLL Clock Rate Select. Transmit Bist Disabled. Differential Serial Output Driver 2 Enable. Differential Serial Output Driver 1 Enable. Transmit Clock Phase Alignment Buffer Reset. Global Latch Enable. Force Global Latch Enable. Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as a NO CONNECT, or GND only. Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a NO CONNECT, or GND only. Primary Differential Serial Data Output. The OUTx1 PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connections. Secondary Differential Serial Data Output. The OUTx2 PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connections.
Device Configuration and Control Bus Signals WREN LVTTL input, asynchronous, internal pull-up LVTTL input asynchronous, internal pull-up
ADDR[3:0]
DATA[4:0]
LVTTL input asynchronous, internal pull-up
Internal Device Configuration Latches TXCKSEL[A..D] Internal Latch[6] TXRATE[A..D] TXBIST[A..D] OE2[A..D] OE1[A..D] PABRST[A..D] GLEN[11..0] FGLEN[2..0] SCANEN2 TMEN3 Analog I/O OUTA1 OUTB1 OUTC1 OUTD1 OUTA2 OUTB2 OUTC2 OUTD2 CML Differential Output Internal Latch[6] Internal Latch[6]
[6]
Internal Latch[6] Internal Latch Internal Latch[6]
[6]
Internal Latch[6] Internal Latch
Factory Test Modes LVTTL input, internal pull-down LVTTL input, internal pull-down
CML Differential Output
Notes 4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). The MID level is usually implemented by not connecting the input (left floating), which allows it to self bias to the proper level. 5. See "Device Configuration and Control Interface" on page 10 for detailed information on the operation of the Configuration Interface. 6. See "Device Configuration and Control Interface" on page 10 for detailed information on the internal latches.
Document #: 38-02104 Rev. *C
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CYV15G0403TB
Pin Definitions (continued) CYV15G0403TB Quad HOTLink II Serializer
Name JTAG Interface TMS TCLK TDO TDI TRST Power VCC GND +3.3V Power. Signal and Power Ground for all internal circuits. reset. While the error remains active, the transmitter for that channel outputs a continuous "1001111000" character (LSB first) to indicate to the remote receiver that an error condition is present in the link. Transmit BIST Each channel contains an internal pattern generator that can be used to validate both the link and device operation. These generators are enabled by the associated TXBISTx latch via the device configuration interface. When enabled, a register in the associated channel becomes a signature pattern generator by logically converting to a Linear Feedback Shift Register (LFSR). This LFSR generates a 511-character sequence. This provides a predictable yet pseudo-random sequence that can be matched to an identical LFSR in the attached Receiver(s). A device reset (RESET sampled LOW) presets the BIST Enable Latches to disable BIST on all channels. All data present at the associated TXDx[9:0] inputs are ignored when BIST is active on that channel. Transmit PLL Clock Multiplier Each Transmit PLL Clock Multiplier accepts a character-rate or half-character-rate external clock at the associated REFCLKx input, and that clock is multiplied by 10 or 20 (as selected by TXRATEx) to generate a bit-rate clock for use by the transmit shifter. It also provides a character-rate clock used by the transmit paths, and outputs this character rate clock as TXCLKOx. Each clock multiplier PLL can accept a REFCLKx input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYV15G0403TB clock multiplier (TXRATEx) and by the level on the associated SPDSELx input. SPDSELx are 3-level select[4] inputs that select one of three operating ranges for the serial data outputs and inputs of the associated channel. The operating serial signaling-rate and LVTTL Input, internal pull-up LVTTL Input, internal pull-down 3-State LVTTL Output LVTTL Input, internal pull-up LVTTL Input, internal pull-up Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high for 5 TCLK cycles, the JTAG test controller is reset. JTAG Test Clock. Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected. Test Data In. JTAG data input port. JTAG reset signal. When asserted (LOW), this input asynchronously resets the JTAG test access port controller. I/O Characteristics Signal Description
CYV15G0403TB HOTLink II Operation
The CYV15G0403TB is a highly configurable, independent clocking, quad-channel serializer designed to support reliable transfer of large quantities of digital video data, using high-speed serial links from multiple sources to multiple destinations. This device supports four 10-bit channels.
CYV15G0403TB Transmit Data Path
Input Register The parallel input bus TXDx[9:0] can be clocked in using TXCLKx (TXCKSELx = 0) or REFCLKx (TXCKSELx = 1). Phase-Align Buffer Data from each Input Register is passed to the associated Phase-Align Buffer, when the TXDx[9:0] input registers are clocked using TXCLKx (TXCKSELx = 0 and TXRATEx = 0). When the TXDx[9:0] input registers are clocked using REFCLKx (TXCKSELx = 1) and REFCLKx is a full-rate clock, the associated Phase Alignment Buffer in the transmit path is bypassed. These buffers are used to absorb clock phase differences between the TXCLKx input clock and the internal character clock for that channel. Once initialized, TXCLKx is allowed to drift in phase as much as 180 degrees. If the input phase of TXCLKx drifts beyond the handling capacity of the Phase Align Buffer, TXERRx is asserted to indicate the loss of data, and remains asserted until the Phase Align Buffer is initialized. The phase of the TXCLKx relative to its associated internal character rate clock is initialized when the configuration latch PABRSTx is written as 0. When the associated TXERRx is deasserted, the Phase Align Buffer is initialized and input characters are correctly captured. If the phase offset, between the initialized location of the input clock and REFCLKx, exceeds the skew handling capabilities of the Phase-Align Buffer, an error is reported on that channel's TXERRx output. This output indicates an error continuously until the Phase-Align Buffer for that channel is Document #: 38-02104 Rev. *C
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CYV15G0403TB
allowable range of REFCLKx frequencies are listed in Table 1. Table 1. Operating Speed Settings SPDSELx LOW MID (Open) HIGH TXRATEx 1 0 1 0 1 0 REFCLKx Frequency (MHz) reserved 19.5-40 20-40 40-80 40-75 80-150 Signaling Rate (Mbps) 195-400 400-800 800-1500
Device Configuration and Control Interface
The CYV15G0403TB is highly configurable via the configuration interface. This interface allows the device to be configured globally or allows each channel to be configured independently. Table 2 on page 11 lists the configuration latches within the device including the initialization value of the latches upon the assertion of RESET. Table 3 on page 12 shows how the latches are mapped in the device. Each row in the Table 3 maps to a 5-bit latch bank. There are 16 such write-only latch banks. When WREN = 0, the logic value in DATA[4:0] is latched to the latch bank specified by the values in ADDR[3:0]. The second column of Table 3 specifies the channels associated with the corresponding latch bank. For example, the first three latch banks (0,1 and 2) consist of configuration bits for channel A. The latch banks 12, 13 and 14 consist of Global configuration bits and the last latch bank (15) is the Mask latch bank that can be configured to perform bit-by-bit configuration. Global Enable Function The global enable function, controlled by the GLENx bits, is a feature that can be used to reduce the number of write operations needed to setup the latch banks. This function is beneficial in systems that use a common configuration in multiple channels. The GLENx bit is present in bit 0 of latch banks 0 through 11 only. Its default value (1) enables the global update of the latch bank's contents. Setting the GLENx bit to 0 disables this functionality. Latch Banks 12, 13, and 14 are used to load values in the related latch banks in a global manner. A write operation to latch bank 12 could do a global write to latch banks 0, 3, 6, and 9 depending on the value of GLENx in these latch banks; latch bank 13 could do a global write to latch banks 1, 4, 7 and 10; and latch banks 14 could do a global write to latch banks 2, 5, 8 and 11. The GLENx bit cannot be modified by a global write operation. Force Global Enable Function FGLENx forces the global update of the target latch banks, but does not change the contents of the GLENx bits. If FGLENx = 1 for the associated global channel, FGLENx forces the global update of the target latch banks. Mask Function An additional latch bank (15) is used as a global mask vector to control the update of the configuration latch banks on a bit-by-bit basis. A logic 1 in a bit location allows for the update of that same location of the target latch bank(s), whereas a logic 0 disables it. The reset value of this latch bank is FFh, thereby making its use optional by default. The mask latch bank is not maskable. The FGLEN functionality is not affected by the bit 0 value of the mask latch bank. Latch Types There are two types of latch banks: static (S) and dynamic (D). Each channel is configured by 2 static and 1 dynamic latch banks. The S type contain those settings that normally do not change for a given application, whereas the D type controls the settings that could change during the application's lifetime. The first and second rows of each channel (address numbers
The REFCLKx inputs are differential inputs with each input internally biased to 1.4V. If the REFCLKx+ input is connected to a TTL, LVTTL, or LVCMOS clock source, the input signal is recognized when it passes through the internally biased reference point. When driven by a single-ended TTL, LVTTL, or LVCMOS clock source, connect the clock source to either the true or complement REFCLKx input, and leave the alternate REFCLKx input open (floating). When both the REFCLKx+ and REFCLKx- inputs are connected, the clock source must be a differential clock. This can either be a differential LVPECL clock that is DC-or AC-coupled or a differential LVTTL or LVCMOS clock. By connecting the REFCLKx- input to an external voltage source, it is possible to adjust the reference point of the REFCLKx+ input for alternate logic levels. When doing so, it is necessary to ensure that the input differential crossing point remains within the parametric range supported by the input. Serial Output Drivers The serial output interface drivers use differential Current Mode Logic (CML) drivers to provide source-matched drivers for 50 transmission lines. These drivers accept data from the Transmit Shifter, which shifts the data out LSB first. These drivers have signal swings equivalent to that of standard PECL drivers, and are capable of driving AC-coupled optical modules or transmission lines. Transmit Channels Enabled Each driver can be enabled or disabled separately via the device configuration interface. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. Note. When a disabled channel (i.e., both outputs disabled) is re-enabled: * data on the serial outputs may not meet all timing specifications for up to 250 s * the state of the phase-align buffer cannot be guaranteed, and a phase-align reset is required if the phase-align buffer is used
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0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The third row of latches for each channel (address numbers 2, 5, 8, and 11) are the dynamic control latches that are associated with enabling dynamic functions within the device. Latch Bank 14 is also useful for those users that do not need the latch-based programmable feature of the device. This latch bank could be used in those applications that do not need to modify the default value of the static latch banks, and that can afford a global (i.e., not independent) control of the dynamic signals. In this case, this feature becomes available when ADDR[3:0] is left unchanged with a value of "1110" and
WREN is left asserted. The signals present in DATA[4:0] effectively become global control pins, and for the latch banks 2, 5, 8 and 11. Static Latch Values There are some latches in the table that have a static value (i.e. 1, 0, or X). The latches that have a `1' or `0' must be configured with their corresponding value each time that their associated latch bank is configured. The latches that have an `X' are don't cares and can be configured with any value.
Table 2. Device Configuration and Control Latch Descriptions Name TXCKSELA TXCKSELB TXCKSELC TXCKSELD TXRATEA TXRATEB TXRATEC TXRATED Signal Description Transmit Clock Select. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input register TXDx[9:0] is clocked by REFCLKx. In this mode, the phase alignment buffer in the transmit path is bypassed. When TXCKSELx = 0, the associated TXCLKx is used to clock in the input register TXDx[9:0]. Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used to select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the associated REFCLKx input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the TXCLKOx output clocks are full-rate clocks and follow the frequency and duty cycle of the associated REFCLKx input. When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx input by 20 to generate the serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the frequency rate of the REFCLKx input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data Inputs are captured using both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx = LOW, is an invalid state and this combination is reserved. Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When TXBISTx = 0, the transmit BIST function is enabled. Secondary Differential Serial Data Output Driver Enable. The initialization value of the OE2x latch = 0. OE2x selects if the OUT2x secondary differential output drivers are enabled or disabled. When OE2x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. Primary Differential Serial Data Output Driver Enable. The initialization value of the OE1x latch = 0. OE1x selects if the OUT1x primary differential output drivers are enabled or disabled. When OE1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When OE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized. PABRST is an asynchronous input, but is sampled by each TXCLKx to synchronize it to the internal clock domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the initialization of the Phase Alignment Buffer. Global Enable. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several channels simultaneously in applications where several channels may have the same configuration. When GLENx = 1 for a given address, that address is allowed to participate in a global configuration. When GLENx = 0 for a given address, that address is disabled from participating in a global configuration. Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global channel, FGLEN forces the global update of the target latch banks. Page 11 of 21
TXBISTA TXBISTB TXBISTC TXBISTD OE2A OE2B OE2C OE2D
OE1A OE1B OE1C OE1D
PABRSTA PABRSTB PABRSTC PABRSTD
GLEN[11..0]
FGLEN[2..0]
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Device Configuration Strategy The following is a series of ordered events needed to load the configuration latches on a per channel basis: 1. Pulse RESET Low after device power-up. This operation resets all four channels. Initialize the JTAG state machine to its reset state as detailed in the JTAG Support section. 2. Set the static latch banks for the target channel. May be performed using a global operation, if the application permits it. 3. Set the dynamic bank of latches for the target channel. Enable the output drivers. May be performed using a global operation, if the application permits it. [Required step.] 4. Reset the Phase Alignment Buffer for the target channel. May be performed using a global operation, if the application permits it. [Optional if phase align buffer is bypassed.]
capability is present only on the LVTTL inputs and outputs and the REFCLKx clock input. The high-speed serial inputs and outputs are not part of the JTAG test chain. To ensure valid device operation after power-up (including non-JTAG operation), the JTAG state machine should also be initialized to a reset state. This should be done in addition to the device reset (using RESET). The JTAG state machine can be initialized using TRST (asserting it LOW and deasserting it or leaving it asserted), or by asserting TMS HIGH for at least 5 consecutive TCLK cycles. This is necessary in order to ensure that the JTAG controller does not enter any of the test modes after device power-up. In this JTAG reset state, the rest of the device will be in normal operation. Note: The order of device reset (using RESET) and JTAG initialization does not matter. 3-Level Select Inputs Each 3-Level select inputs reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11 respectively JTAG ID The JTAG device ID for the CYV15G0403TB is `0C810069'x.
JTAG Support
The CYV15G0403TB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This Table 3. Device Control Latch Configuration Table
ADDR 0 (0000b) 1 (0001b) 2 (0010b) 3 (0011b) 4 (0100b) 5 (0101b) 6 (0110b) 7 (0111b) 8 (1000b) 9 (1001b) 10 (1010b) 11 (1011b) 12 (1100b) 13 (1101b) 14 (1110b) 15 (1111b) Channel A A A B B B C C C D D D GLOBAL GLOBAL GLOBAL MASK Type S S D S S D S S D S S D S S D D DATA4 X X TXBISTA X X TXBISTB X X TXBISTC X X TXBISTD X X TXBISTGL D4 DATA3 X 0 OE2A X 0 OE2B X 0 OE2C X 0 OE2D X 0 OE2GL D3
DATA2 0 TXCKSELA OE1A 0 TXCKSELB OE1B 0 TXCKSELC OE1C 0 TXCKSELD OE1D 0 TXCKSELGL OE1GL D2
DATA1 X TXRATEA PABRSTA X TXRATEB PABRSTB X TXRATEC PABRSTC X TXRATED PABRSTD X TXRATEGL PABRSTGL D1
DATA0 GLEN0 GLEN1 GLEN2 GLEN3 GLEN4 GLEN5 GLEN6 GLEN7 GLEN8 GLEN9 GLEN10 GLEN11 FGLEN0 FGLEN1 FGLEN2 D0
Reset Value 11111 01101 10011 11111 01101 10011 11111 01101 10011 11111 01101 10011 N/A N/A N/A 11111
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Maximum Ratings
Above which the useful life may be impaired. User guidelines only, not tested Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +3.8V DC Voltage Applied to LVTTL Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Output Current into LVTTL Outputs (LOW)..................60 mA DC Input Voltage....................................-0.5V to VCC + 0.5V
Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYV15G0403TB requires one power-supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC +3.3V 5%
CYV15G0403TB DC Electrical Characteristics
Parameter LVTTL-compatible Outputs VOHT VOLT IOST IOZL VIHT VILT IIHT IILT IIHPDT IILPUT VDIFF[8] VIHHP VILLP VCOMREF VIHH VIMM VILL IIHH IIMM IILL VOHC
[9]
Description Output HIGH Voltage Output LOW Voltage Output Short Circuit Current High-Z Output Leakage Current Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Input HIGH Current with internal pull-down Input LOW Current with internal pull-up Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW voltage Common Mode Range Three-Level Input HIGH Voltage Three-Level Input MID Voltage Three-Level Input LOW Voltage Input HIGH Current Input MID current Input LOW current Output HIGH Voltage (Vcc Referenced)
Test Conditions IOH = -4 mA, VCC = Min. IOL = 4 mA, VCC = Min. VOUT = 0V[7], VCC = 3.3V VOUT = 0V, VCC
Min. 2.4
Max.
Unit V
0.4 -20 -20 2.0 -0.5 -100 20 VCC + 0.3 0.8 1.5 +40 -1.5 -40 +200 -200 400 1.2 0.0 1.0 VCC VCC VCC/2 VCC - 1.2V VCC 0.53 * VCC 0.13 * VCC 200 -50 50 -200 VCC - 0.5 VCC - 0.2
V mA A V V mA A mA A A A mV V V V V V V A A A V
LVTTL-compatible Inputs
REFCLKx Input, VIN = VCC Other Inputs, VIN = VCC REFCLKx Input, VIN = 0.0V Other Inputs, VIN = 0.0V VIN = VCC VIN = 0.0V
LVDIFF Inputs: REFCLKx
3-Level Inputs Min. VCC Max. Min. VCC Max. Min. VCC Max. VIN = VCC VIN = VCC/2 VIN = GND 100 differential load 0.87 * VCC 0.47 * VCC 0.0
Differential CML Serial Outputs: OUTA1, OUTA2, OUTB1, OUTB2, OUTC1, OUTC2, OUTD1, OUTD2 VCC - 0.2 V 150 differential load VCC - 0.5 Notes 7. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 8. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the true (+) input is more positive than the complement (-) input. A logic-0 exists when the complement (-) input is more positive than true (+) input. 9. The common mode range defines the allowable range of REFCLKx+ and REFCLKx- when REFCLKx+ = REFCLKx-. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. Document #: 38-02104 Rev. *C Page 13 of 21
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CYV15G0403TB DC Electrical Characteristics (continued)
Parameter VOLC VODIF Description Output LOW Voltage (VCC Referenced) Output Differential Voltage |(OUT+) - (OUT-)| Test Conditions 100 differential load 150 differential load 100 differential load 150 differential load REFCLKx = Commercial MAX REFCLKx = Commercial 125 MHz Min. VCC - 1.4 VCC - 1.4 450 560 Typ. 640 610 Max. VCC - 0.7 VCC - 0.7 900 1000 Max. 820 790 mA mA Unit V V mV mV
Power Supply ICC [10,11] ICC [10,11] Max Power Supply Current Typical Power Supply Current
AC Test Loads and Waveforms
3.3V R1 R1 = 590 R2 = 435 CL CL 7 pF (Includes fixture and probe capacitance) RL = 100 (Includes fixture and probe capacitance)
[12] (b) CML Output Test Load
RL
R2
[12]
(a) LVTTL Output Test Load
3.0V Vth = 1.4V GND 1 ns 2.0V 0.8V 2.0V 0.8V
VIHE Vth = 1.4V VILE 1 ns 20%
VIHE 80% VILE 80% 20% 270 ps
270 ps
(c) LVTTL Input Test Waveform
[13]
(d) CML/LVPECL Input Test Waveform
CYV15G0403TB AC Electrical Characteristics
Parameter fTS tTXCLK tTXCLKH[14] tTXCLKL[14] tTXCLKR [14, 15, 16, 17] tTXCLKF [14, 15, 16, 17] tTXDS tTXDH fTOS Description TXCLKx Clock Cycle Frequency TXCLKx Period=1/fTS TXCLKx HIGH Time TXCLKx LOW Time TXCLKx Rise Time TXCLKx Fall Time Transmit Data Set-up Time to TXCLKx (TXCKSELx = 0) Transmit Data Hold Time from TXCLKx (TXCKSELx = 0) TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency Min. 19.5 6.66 2.2 2.2 0.2 0.2 2.2 1.0 19.5 150 1.7 1.7 Max. 150 51.28 Unit MHz ns ns ns ns ns ns ns MHz CYV15G0403TB Transmitter LVTTL Switching Characteristics Over the Operating Range
Notes 10. Maximum ICC is measured with VCC = MAX, TA = 25C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and outputs unloaded. 11. Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25C, with all channels enabled and one Serial Line Driver per channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down. 12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage. 14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested. 15. The ratio of rise time to falling time must not vary by greater than 2:1. 16. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time. 17. All transmit AC timing parameters measured with 1 ns typical rise time and fall time.
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CYV15G0403TB AC Electrical Characteristics (continued)
Parameter tTXCLKO tTXCLKOD fREF tREFCLK tREFH tREFL tREFD[18] tREFR
[14, 15, 16, 17]
Description TXCLKOx Period = 1/fTOS TXCLKO Duty Cycle centered at 60% HIGH time REFCLKx Clock Frequency REFCLKx Period = 1/fREF REFCLKx HIGH Time (TXRATEx = 1)(Half Rate) REFCLKx HIGH Time (TXRATEx = 0)(Full Rate) REFCLKx LOW Time (TXRATEx = 1)(Half Rate) REFCLKx LOW Time (TXRATEx = 0)(Full Rate) REFCLKx Duty Cycle REFCLKx Rise Time (20%-80%) REFCLKx Fall Time (20%-80%) Transmit Data Set-up Time to REFCLKx - Full Rate (TXRATEx = 0, TXCKSELx = 1) Transmit Data Set-up Time to REFCLKx - Half Rate (TXRATEx = 1, TXCKSELx = 1)
Min. 6.66 -1.9 19.5 6.6 5.9 2.9[14] 5.9 2.9
[14]
Max. 51.28 0 150 51.28
Unit ns ns MHz ns ns ns ns ns
CYV15G0403TB REFCLKx Switching Characteristics Over the Operating Range
30
70 2 2
% ns ns ns ns ns ns
tREFF[14, 15, 16, 17] tTREFDS
2.4 2.3 1.0 1.6
tTREFDH
Transmit Data Hold Time from REFCLKx - Full Rate (TXRATEx = 0, TXCKSELx = 1) Transmit Data Hold Time from REFCLKx - Half Rate (TXRATEx = 1, TXCKSELx = 1)
CYV15G0403TB Bus Configuration Write Timing Characteristics Over the Operating Range tDATAH tDATAS tWRENP fTCLK tTCLK tRST Parameter tB tRISE[14] Bit Time CML Output Rise Time 20-80% (CML Test Load) SPDSELx = HIGH SPDSELx = MID SPDSELx =LOW tFALL[14] CML Output Fall Time 80-20% (CML Test Load) SPDSELx = HIGH SPDSELx = MID SPDSELx =LOW Bus Configuration Data Hold Bus Configuration Data Setup Bus Configuration WREN Pulse Width JTAG Test Clock Frequency JTAG Test Clock Period Device RESET Pulse Width Description Condition 50 30 Min. 660 50 100 180 50 100 180 Max. 5128 270 500 1000 270 500 1000 0 10 10 20 ns ns ns MHz ns ns Unit ps ps ps ps ps ps ps
CYV15G0403TB JTAG Test Clock Characteristics Over the Operating Range
CYV15G0403TB Device RESET Characteristics Over the Operating Range CYV15G0403TB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range
Note 18. The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the REFCLKx duty cycle cannot be as large as 30%-70%.
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PLL Characteristics
Parameter tJTGENSD[14, 19] tJTGENHD[14, 19] tTXLOCK Description Transmit Jitter Generation - SD Data Rate Transmit Jitter Generation - HD Data Rate Transmit PLL lock to REFCLKx Condition REFCLKx = 27 MHz REFCLKx = 148.5 MHz Min. Typ. 200 76 200 Max. Unit ps ps s CYV15G0403TB Transmitter Output PLL Characteristics
Capacitance [14]
Parameter CINTTL CINPECL Description TTL Input Capacitance PECL input Capacitance Test Conditions TA = 25C, f0 = 1 MHz, VCC = 3.3V TA = 25C, f0 = 1 MHz, VCC = 3.3V Max. 7 4 Unit pF pF
CYV15G0403TB HOTLink II Transmitter Switching Waveforms
Transmit Interface Write Timing TXCLKx selected
TXCLKx
tTXCLK tTXCLKH tTXCLKL
tTXDS
TXDx[9:0]
tTXDH
Transmit Interface Write Timing REFCLKx selected TXRATEx = 0
REFCLKx
tREFCLK tREFH tREFL
tTREFDS
TXDx[9:0]
tTREFDH
Transmit Interface Write Timing REFCLKx selected TXRATEx = 1
REFCLKx
tREFCLK tREFH tREFL
Note 20
tTREFDS
TXDx[9:0]
tTREFDH
tTREFDS
tTREFDH
Notes 19. While sending BIST data at the corresponding data rate, after 10,000 histogram hits on a digital sampling oscilloscope, time referenced to REFCLKx input. 20. When REFCLKx is configured for half-rate operation (TXRATEx = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using both the rising and falling edges of REFCLKx.
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CYV15G0403TB HOTLink II Transmitter Switching Waveforms (continued)
Transmit Interface TXCLKOx Timing TXRATEx = 1
REFCLKx
tREFCLK tREFH tREFL
Note 21
tTXCLKO
Note 22
TXCLKOx (internal)
Transmit Interface TXCLKOx Timing tREFH TXRATEx = 0
REFCLKx
tREFCLK tREFL
Note 21
Note 22
tTXCLKO
TXCLKOx
CYV15G0403TB HOTLink II Bus Configuration Switching Waveforms
Bus Configuration Write Timing
ADDR[3:0]
DATA[4:0]
tWRENP
WREN
tDATAS tDATAH
Notes 21. The TXCLKOx output remains at the character rate regardless of the state of TXRATEx and does not follow the duty cycle of REFCLKx. 22. The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx input.
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Table 4. Package Coordinate Signal Allocation Ball ID A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C01 C02 C03 Signal Name NC OUTC1- NC OUTC2- VCC NC OUTD1- GND GND OUTD2- GND OUTA1- GND GND OUTA2- VCC VCC OUTB1- VCC OUTB2- VCC OUTC1+ VCC OUTC2+ VCC VCC OUTD1+ GND NC OUTD2+ NC OUTA1+ GND NC OUTA2+ VCC NC OUTB1+ NC OUTB2+ TDI TMS VCC Signal Type NO CONNECT CML OUT NO CONNECT CML OUT POWER NO CONNECT CML OUT GROUND GROUND CML OUT GROUND CML OUT GROUND GROUND CML OUT POWER POWER CML OUT POWER CML OUT POWER CML OUT POWER CML OUT POWER POWER CML OUT GROUND NO CONNECT CML OUT NO CONNECT CML OUT GROUND NO CONNECT CML OUT POWER NO CONNECT CML OUT NO CONNECT CML OUT LVTTL IN PU LVTTL IN PU POWER Ball ID C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E01 E02 E03 E04 E17 E18 E19 E20 F01 Signal Name NC GND NC NC DATA[3] DATA[1] GND NC SPDSELD VCC NC TRST GND TDO TCLK RESET VCC VCC VCC VCC SPDSELC GND GND DATA[4] DATA[2] DATA[0] GND GND NC VCC NC NC SCANEN2 TMEN3 VCC VCC VCC VCC VCC VCC VCC VCC NC Signal Type NO CONNECT GROUND NO CONNECT NO CONNECT LVTTL IN PU LVTTL IN PU GROUND NO CONNECT 3-LEVEL SEL POWER NO CONNECT LVTTL IN PU GROUND LVTTL 3-S OUT LVTTL IN PD LVTTL IN PU POWER POWER POWER POWER 3-LEVEL SEL GROUND GROUND LVTTL IN PU LVTTL IN PU LVTTL IN PU GROUND GROUND NO CONNECT POWER NO CONNECT NO CONNECT LVTTL IN PD LVTTL IN PD POWER POWER POWER POWER POWER POWER POWER POWER NO CONNECT Ball ID F17 F18 F19 F20 G01 G02 G03 G04 G17 G18 G19 G20 H01 H02 H03 H04 H17 H18 H19 H20 J01 J02 J03 J04 J17 J18 J19 J20 K01 K02 K03 K04 K17 K18 K19 K20 L01 L02 L03 L04 L17 L18 L19 Signal Name NC NC TXCLKOB NC TXDC[7] WREN TXDC[4] TXDC[1] SPDSELB NC SPDSELA NC GND GND GND GND GND GND GND GND TXDC[9] TXDC[5] TXDC[2] TXDC[3] NC NC NC NC NC REFCLKC- TXDC[8] TXCLKC NC NC NC NC NC REFCLKC+ NC TXDC[6] NC NC NC Signal Type NO CONNECT NO CONNECT LVTTL OUT NO CONNECT LVTTL IN LVTTL IN PU LVTTL IN LVTTL IN 3-LEVEL SEL NO CONNECT 3-LEVEL SEL NO CONNECT GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND LVTTL IN LVTTL IN LVTTL IN LVTTL IN NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT PECL IN LVTTL IN LVTTL IN PD NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT PECL IN NO CONNECT LVTTL IN NO CONNECT NO CONNECT NO CONNECT Page 18 of 21
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CYV15G0403TB
Table 4. Package Coordinate Signal Allocation (continued) Ball ID C04 C05 C06 M03 M04 M17 M18 M19 M20 N01 N02 N03 N04 N17 N18 N19 N20 P01 P02 P03 P04 P17 P18 P19 P20 R01 R02 R03 R04 R17 R18 R19 R20 T01 T02 T03 T04 T17 T18 T19 T20 U01 U02 Signal Name VCC VCC NC NC TXERRC REFCLKB+ REFCLKB- TXERRB TXCLKB GND GND GND GND GND GND GND GND NC NC NC NC TXDB[5] TXDB[4] TXDB[3] TXDB[2] NC TXCLKOC NC NC TXDB[1] TXDB[0] TXDB[9] TXDB[7] VCC VCC VCC VCC VCC VCC VCC VCC TXDD[0] TXDD[1] Signal Type POWER POWER NO CONNECT NO CONNECT LVTTL OUT PECL IN PECL IN LVTTL OUT LVTTL IN PD GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND NO CONNECT NO CONNECT NO CONNECT NO CONNECT LVTTL IN LVTTL IN LVTTL IN LVTTL IN NO CONNECT LVTTL OUT NO CONNECT NO CONNECT LVTTL IN LVTTL IN LVTTL IN LVTTL IN POWER POWER POWER POWER POWER POWER POWER POWER LVTTL IN LVTTL IN Ball ID F02 F03 F04 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W01 W02 Signal Name NC TXDC[0] NC TXDD[2] TXDD[9] VCC NC NC GND TXDA[9] ADDR [0] REFCLKD- TXDA[1] GND TXDA[4] TXDA[8] VCC NC TXDB[8] NC NC TXDD[3] TXDD[4] TXDD[8] NC VCC NC NC GND NC ADDR [2] REFCLKD+ TXCLKOA GND TXDA[3] TXDA[7] VCC NC NC NC NC TXDD[5] TXDD[7] Signal Type NO CONNECT LVTTL IN NO CONNECT LVTTL IN LVTTL IN POWER NO CONNECT NO CONNECT GROUND LVTTL IN LVTTL IN PU PECL IN LVTTL IN GROUND LVTTL IN LVTTL IN POWER NO CONNECT LVTTL IN NO CONNECT NO CONNECT LVTTL IN LVTTL IN LVTTL IN NO CONNECT POWER NO CONNECT NO CONNECT GROUND NO CONNECT LVTTL IN PU PECL IN LVTTL OUT GROUND LVTTL IN LVTTL IN POWER NO CONNECT NO CONNECT NO CONNECT NO CONNECT LVTTL IN LVTTL IN Page 19 of 21 Ball ID L20 M01 M02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name TXDB[6] NC NC NC NC VCC NC NC GND ADDR [3] ADDR [1] NC TXERRA GND TXDA[2] TXDA[6] VCC NC REFCLKA+ NC NC TXDD[6] TXCLKD NC NC VCC NC NC GND TXCLKOD NC TXCLKA NC GND TXDA[0] TXDA[5] VCC TXERRD REFCLKA- NC NC Signal Type LVTTL IN NO CONNECT NO CONNECT NO CONNECT NO CONNECT POWER NO CONNECT NO CONNECT GROUND LVTTL IN PU LVTTL IN PU NO CONNECT LVTTL OUT GROUND LVTTL IN LVTTL IN POWER NO CONNECT PECL IN NO CONNECT NO CONNECT LVTTL IN LVTTL IN PD NO CONNECT NO CONNECT POWER NO CONNECT NO CONNECT GROUND LVTTL OUT NO CONNECT LVTTL IN PD NO CONNECT GROUND LVTTL IN LVTTL IN POWER LVTTL OUT PECL IN NO CONNECT NO CONNECT
Document #: 38-02104 Rev. *C
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CYV15G0403TB
Ordering Information
Speed Standard Standard Ordering Code CYV15G0403TB-BGC CYV15G0403TB-BGXC Package Name BL256 BL256 Package Type 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Operating Range Commercial Commercial
Package Diagram
Figure 2. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256
TOP VIEW
27.000.13 A1 CORNER I.D.
0.20(4X) A O0.15 M C O0.30 M C O0.750.15(256X)
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y
BOTTOM VIEW (BALL SIDE)
A B
24.13
A1 CORNER I.D.
R 2.5 Max (4X)
27.000.13
12.065 1.27 24.13
A
B 1.570.175 0.97 REF. 0.15 C
0.50 MIN.
A
0.600.10 C
26 TYP.
0.15
C
SEATING PLANE
0.20 MIN TOP OF MOLD COMPOUND TO TOP OF BALLS
SIDE VIEW
SECTION A-A
51-85123-*E
HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-02104 Rev. *C
Page 20 of 21
(c) Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CYV15G0403TB
Document History Page
Document Title: CYV15G0403TB Independent Clock Quad HOTLink IITM Serializer Document Number: 38-02104 REV. ** *A *B *C ECN NO. 246850 338721 384307 1034120 ISSUE DATE See ECN See ECN See ECN See ECN ORIG. OF CHANGE FRE SUA AGT UKK New Data Sheet Added Pb-Free package option availability Revised setup and hold times (tTXDH, tTREFDS, tTREFDH) Added clarification for the necessity of JTAG controller reset and the methods to implement it. DESCRIPTION OF CHANGE
Document #: 38-02104 Rev. *C
Page 21 of 21
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